HIL and Design Validation Systems
Averna is recognized as a premier developer, integrator, and supporter of Hardware-In-the-Loop (HIL) and design validation systems for a vast range of military and commercial aerospace and defense applications.
Based on the scalable PXI platform, our HIL systems integrate simulation models with real-time test systems to help engineers reduce design cycle and prototyping costs, as well as system development time. These solutions provide simultaneous I/O for a wide range of analog and digital signals interfaced with simulation models through low-latency reflective memory technology.
Obtain the following benefits for HIL and design validation:
- Extreme data integrity
- Determinism
- Extensive analysis capabilities
- Fast data throughput
- Low latency
Certified for ISO, CSIA, and the Controlled Good Program, and compliant with all necessary regulatory and security standards including ITAR, Averna has a decade of experience in assuring superior validation services in an industry where it counts most.
Applications for H-I-L
MIL-STD-1553 CompactRIO™ Development
The MIL-STD-1553 CompactRIO™ Module operates in Bus Controller (BC), Remote Terminal (RT), or Bus Monitor (BM) mode. It includes a dual-redundant bus BC/RT/BM 1553 channel in a single-slot cRIO module that can be installed in the cRIO 4-slot or 8-slot reconfigurable I/O (RIO) FPGA chassis. It provides a choice of RT buffering modes, a selective message monitor, 64K words of RAM, and many other functions and features of the advanced bus controller architecture that handles the 1553 protocol physical layer details.
