IEEE-1394 Software Products
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| IEEE-1394 Software Map |
Averna's suite of IEEE-1394 software solutions provides efficient and flexible connectivity for applications and
devices over the IEEE-1394/FireWire® bus.
Engineers rely on these software solutions to customize Averna's IEEE-1394 hardware products to specific
requirements for their embedded systems.
IEEE-1394 Low Level API
Averna's IEEE-1394 LLA is a low-level communication library that provides direct access to hardware chipsets and
enables full control over the IEEE-1394 bus.
The LLA can act as either a hardware driver for 1394 adapters to ease the development of communication systems, or it
can deliver enhanced performance for the 1394 serial bus, when required by bandwidth-intensive applications. When used
in this manner, the LLA library forms part of a device driver for communication processing in the operating
system's kernel mode.
This high-performance solution allows for very low latency, and overcomes packet size limits delineated by the IEEE-1394 protocol.
Features
- Asynchronous and isochronous transmission mechanisms
- Buffer-fill mode for isochronous reception
- Support for OHCI-compliant chipsets
- Zero-copy API
- Available for VxWorks, QNX, Integrity, Windows, LabWindows RT and others upon request
Benefits
- Enables full control of the IEEE-1394 bus
- Ideal for closed IEEE-1394 buses (AS5643)
- Overcomes the limits imposed by the IEEE-1394 protocol regarding packet sizes
- Low latency
Click here to download “IEEE-1394 LLA” datasheet
IEEE-1394 IP-over-1394
Averna's IPv4-over-1394 software provides efficient IPv4 communication over the IEEE-1394/FireWire® bus.
Averna has developed three versions to better suit individual requirements:
Click here to download “IPv4-over-1394” datasheet
IP-over-Stack
This is a fully compliant version for when interoperability with other IP-over-1394 implementation is required, and when
the application must interface with other protocols.
IP-over-LLA (low-level API)
Averna's IP-over-LLA solution focuses on providing strictly IP-over-1394 communication using minimal footprint and
CPU power, while ensuring maximum throughput.
Click here to download “IEEE-1394 IP-over-LLA” datasheet
FAST IP-over-LLA
A custom version of the IP-over-LLA, this solution is targeted at closed environment projects. It allows for the removal
of unused features, making the code lighter and more efficient at the cost of no longer being fully compliant with
IEEE-1394 and RFCs. This optimization is only possible if all 1394 nodes in the project use the FAST IP-over-LLA
version.
Features
- IP-over-1394 communication compliant with RFC 768 (UDP), RFC 791 (IP), RFC 2734 (IPv4-over-1394) and IEEE-1394
- BSD 4.4 socket API
- Real zero-copy communication including fragmentation, re-assembly and an API similar to BSD 4.4 (IP-over-LLA only)
- Dedicated to IP-over-1394 operations (IP-over-LLA only)
- Available on major RTOS and CPU, can be ported to additional RTOSs, CPUs, or IP stacks
Options
- Redundancy
- Fault-tolerance
- UDP/IP communication with reliability equivalent to TCP/IP communications
- TCP, ICMP, and other IP-based protocols
Benefits
- Low CPU bandwidth usage (IP-over-LLA only)
- Small memory footprint (IP-over-LLA only)
- High throughput on 1394 link, up to 800 Mbps
- Customizable IP-over-LLA for higher performance in closed environments (FAST IP-over-LLA only)
- Complete training available (1, 2 ,or 3-day training)
IEEE-1394 Stack
This modular stack's solid Application Programming Interface (API) provides all the functionality users need to
harness the power of IEEE-1394 serial bus protocol transactions. Powerful and flexible, the IEEE-1394 Stack is designed
for embedded systems, and supports most generic Real-Time Operating Systems (RTOS).
Features
- CSR mandatory read/write/lock accesses
- Isochronous/asynchronous operations
- Serial bus management
- Concurrent transactions handling
- Cycle Master, Isochronous Manager, and Bus Manager capable
- Dynamic building of the configuration ROM
- Compliant with IEEE-1394a-2000 and 1394b standards
- Supports most generic RTOS
- Zero-copy API
- Available for VxWorks, QNX and others upon request
Benefits
- Supports multiple applications
- Bandwidth and channel reservation API
- Configurable to reduce code size and memory usage
- Device driver interface to allow inter-process communication (on QNX)
- Common foundation for all IEEE-1394 protocols
- Support direct memory mapping to IEEE-1394 addressing (DMA transfer with OHCI physical requests
Click here to download “IEEE-1394 Stack” datasheet
SBP-2 Protocol
Typically used for peripherals such as hard disks, printers, scanners, and other storage devices, the SBP-2 protocol
provides a command and data transport mechanism that exports command processing and queuing to the peripheral, creating
a powerful scriptable DMA device. This means that the device (target) can read commands and read/write data directly
from the CPU memory (initiator), and then take the appropriate action.
Features
- Compliant with ANSI NCITS 325-1998 (SBP-2 Protocol) and IEEE-1394
- Zero-copy communication
- Available on major RTOS and CPU, can be ported to additional RTOS or CPU
- Available on request: SBP-2 Target for OHCI chipset
Benefits
- Enables direct read/write from CPU
- High throughput on IEEE-1394 link
Typical applications:
- Printers
- Hard drives
- Scanners
Click here to download “IEEE-1394 High Level Protocols” datasheet
IIDC Application Programming Interface
Averna's IEEE-1394 IIDC Application Programming Interface (API) controls defined features of IIDC-based digital
cameras, and allows a user without in-depth expertise in IEEE-1394 connectivity to capture image data. This API is
equipped with a basic set of 1394 function calls that communicate between the user application and the IIDC-compliant camera.
An IIDC-compliant camera is most often a peripheral for a personal computer or workstation. Another node on the 1394
bus, such as the computer running an IIDC application, acts as the camera controller. Before the camera can perform any
action, it must be accessed and configured by this camera controller. IIDC cameras are passive devices, and initiate no
actions on their own.
Typical applications:
- Industrial digital cameras
- Vision systems
Click here to download “Digital Camera Protocol” datasheet
IEEE-1394b FPGA Link Layer Core
Averna's IEEE-1394b FPGA Link Layer Core is a highly scalable core module developed for engineers working with
multimedia-equipped embedded systems. It provides transmission speeds of up to 800 Mbps, which is the maximum throughput
currently available through the 1394b standard.
The reprogrammable FPGA aspect means that dedicated processing tasks can be run in parallel and design can be integrated
on the same chip for faster simulation times and lower production costs. Averna's FPGA Link Layer Core provides
hardware-timed speed and reliability for bandwidth-hungry applications.
Features
- 800 Mbps transmission speed
- Fewer than 2000 flip-flops for a fully functional version
- Four isochronous reception filters
- Fully tested on Virtex2, Virtex 4LX, Virtex 5LX, and Stratix-II devices
- Evaluation kit available \for Xilinx
Benefits
- FPGA's reprogrammable aspect allows for design to be integrated on single chip
- Faster simulation times, lower production costs
- Speed is hardware-timed
Click here to download “IEEE-1394b FPGA link layer core” datasheet
